Magnetic shielding of STT-MRAM in multichip packaging and method of manufacturing the same
US10361162B1 · kind B1 · utility
3Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 23, 2018 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Jan 23, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3025
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Methodologies and an apparatus for enabling magnetic shielding of stand alone MRAM are provided. Embodiments include placing MRAM dies and logic dies on a first surface of a mold frame; forming a top magnetic shield over top and side surfaces of the MRAM dies; forming a mold cover over the MRAM dies, FinFET dies and mold frame; removing the mold frame to expose a bottom surface of the MRAM dies and FinFET dies; and forming a bottom magnetic shield over the bottom surface of the MRAM dies.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.