Semiconductor package having a molding layer including a molding cavity and method of fabricating the same
US10361177B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 24, 2018 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Apr 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18161
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed are a semiconductor package and a method of fabricating the same. The semiconductor package comprises a lower semiconductor chip on a lower substrate, a lower molding layer covering the lower semiconductor chip on the lower substrate and including a molding cavity that extends toward the lower semiconductor chip from a top surface of the lower molding layer, an interposer substrate on the top surface of the lower molding layer and including a substrate opening that penetrates the interposer substrate and overlaps the molding cavity, and an upper package on the interposer substrate. The molding cavity has a floor surface spaced apart from the upper package across a substantially hollow space.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.