Method for fabricating a JFET transistor within an integrated circuit and corresponding integrated circuit
US10361188B2 · kind B2 · utility
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9Claims
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Key dates
| Filing date | Apr 20, 2016 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Jan 2, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/85
Abstract
An integrated circuit of the BiCMOS type includes at least one vertical junction field-effect transistor. The vertical junction field-effect transistor is formed to include a channel region having a critical dimension of active surface that is controlled by photolithography.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.