Memory cells and memory arrays
US10361204B2 · kind B2 · utility
0Cited by
24References
3Claims
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Assignee
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Key dates
| Filing date | Jun 12, 2018 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Jun 12, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Some embodiments include a memory cell having first, second and third transistors, with the second and third transistors being vertically displaced relative to one another. The memory cell has a semiconductor pillar extending along the second and third transistors, with the semiconductor pillar containing channel regions and source/drain regions of the second and third transistors. A capacitor may be electrically coupled between a source/drain region of the first transistor and a gate of the second transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.