Three dimensional memory device containing multilayer wordline barrier films and method of making thereof
US10361213B2 · kind B2 · utility
20Cited by
56References
11Claims
0Family size
Assignee
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Key dates
| Filing date | Apr 10, 2017 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | May 9, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/037
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Memory stack structures are formed through an alternating stack of insulating layers and sacrificial material layers. Backside recesses are formed by removal of the sacrificial material layers selective to the insulating layers and the memory stack structures. A barrier layer stack including a crystalline electrically conductive barrier layer and an amorphous barrier layer is formed in the backside recesses prior to formation of a metal fill material layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.