Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems
US10361471B2 · kind B2 · utility
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199References
15Claims
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Key dates
| Filing date | Mar 18, 2016 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Jan 29, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K1/00
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
Structures and methods for interconnects and associated alignment and assembly mechanisms for and between chips, components, and 3D systems.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.