Switch linearization by compensation of a field-effect transistor
US10361697B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2017 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Dec 22, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B2001/0408
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed herein are systems and methods for reducing intermodulation distortion (IMD) in switches using parallel distorter circuits. A switch circuit can include having a switch arm and a distorter arm that is configured to act as a compensation circuit to compensate for non-linearities in the switch arm. The switch circuit can include a plurality of FETs in the switch arm configured to provide switching functionality. The distorter arm is configured to compensate for a non-linearity effect generated by the FETs of the switch arm when it is in an ON state. The distorter arm is configured to compensate for the non-linearity effect generated by the switch arm independent of the frequency of the signal received by the switch arm. Various configurations of switch arms and distorter arms can be implemented to reduce harmonic distortion as well as intermodulation distortion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.