Memory modules, memory systems including the same, and methods of calibrating multi-die impedance of the memory modules
US10361699B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2018 |
| Grant date | Jul 23, 2019 |
| Priority date | — |
| Expiry date | Mar 15, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4093
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory module includes an external resistor and a plurality of memory devices commonly connected to the external resistor. Each of the memory devices includes a first reception pad and a first transmission pad. The first reception pad is associated with receiving an impedance calibration command and the first transmission pad is associated with transmitting the impedance calibration command. Each of the memory devices transfers the impedance calibration command to a first memory device which is selected as a master among the plurality of memory devices through a ring topology. The first memory device performs an impedance calibration operation, determines a resistance and a target output high level voltage of an output driver in response to the impedance calibration command, and transfers the impedance calibration command to a second memory device after performing the impedance calibration operation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.