Yoon-Joo Eom
18Patents
4h-index
22Co-inventors
56Inventor score
Filing activity: Sep 12, 2012 → Oct 24, 2023
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US10255969B2 | Multi channel semiconductor device having multi dies and operation method thereof | Physics | 43 | Active |
| US10361699B2 | Memory modules, memory systems including the same, and methods of calibrating multi-die impedance of the memory modules | Physics | 19 | Active |
| US9105317B2 | Memory system capable of calibrating output voltage level of semiconductor memory device and method of calibrating output voltage level of semiconductor memory device | Physics | 7 | Active |
| US9183902B2 | Input data alignment circuit and semiconductor device including the same | Physics | 6 | Active |
| US9899075B2 | Multi channel semiconductor device having multi dies and operation method thereof | Physics | 4 | Active |
| US9209764B2 | Small signal receiver and integrated circuit including the same | Electricity | 3 | Active |
| US10062430B2 | Multi channel semiconductor device having multi dies and operation method thereof | Physics | 3 | Active |
| US11195571B2 | Memory device and method with data input | Physics | 2 | Active |
| US9196325B2 | Integrated circuit with on die termination and reference voltage generation and methods of using the same | Physics | 2 | Active |
| US10666467B2 | Memory device and operation method thereof | Physics | 1 | Active |
| US9030262B2 | Input receiver circuit having single-to-differential amplifier, and semiconductor device including the same | Electricity | 1 | Active |
| US9355706B2 | Output circuit for implementing high speed data transmition | Physics | 0 | Active |
| US9742355B2 | Buffer circuit robust to variation of reference voltage signal | Electricity | 0 | Active |
| US11721391B2 | Multi channel semiconductor device having multi dies and operation method thereof | Physics | 0 | Active |
| US11443794B2 | Multi channel semiconductor device having multi dies and operation method thereof | Physics | 0 | Active |
| US11862234B2 | Memory device and operation method thereof | Physics | 0 | Active |
| US8934317B2 | Semiconductor memory devices having internal clock signals and memory systems including such memory devices | Physics | 0 | Active |
| US12154616B2 | Memory device and operation method thereof | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.