I/O writes with cache steering

US10366027B2 · kind B2 · utility

Assignees

• Advanced Micro Devices, Inc. · US
• ATI Technologies ULC · CA

Inventors

• Eric Christopher Morton · Austin, US
• Elizabeth M. Cooper · Los Gatos, US
• William L. Walker · Fort Collins, US
• Douglas Benson Hunt · Fort Collins, US
• Richard Martin Born · Fort Collins, US
• Richard H. Lee · San Clemente, US
• Paul C. Miranda · Austin, US
• Philip Ng · Thornhill, CA
• Paul James Moyer · Fort Collins, US

Key dates

• Filing date: Nov 29, 2017
• Grant date: Jul 30, 2019
• Expiry date: Nov 29, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2212/621
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A method for steering data for an I/O write operation includes, in response to receiving the I/O write operation, identifying, at an interconnect fabric, a cache of one of a plurality of compute complexes as a target cache for steering the data based on at least one of: a software-provided steering indicator, a steering configuration implemented at boot initialization, and coherency information for a cacheline associated with the data. The method further includes directing, via the interconnect fabric, the identified target cache to cache the data from the I/O write operation. The data is temporarily buffered at the interconnect fabric, and if the target cache attempts to fetch the data while the data is still buffered at the interconnect fabric, the interconnect fabric provides a copy of the buffered data in response to the fetch operation instead of initiating a memory access operation to obtain the data from memory.