Programming for electronic memories
US10366752B2 · kind B2 · utility
2Cited by
14References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2017 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Dec 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2213/77
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Memory circuitry comprises memory cells having two terminals and a feedback path connected between the two terminals. The feedback path is used to adaptively amplify identical programming pulses that serve to change memory states of the memory cell, and the amplification is based on a current resistive level of the memory cell, which may for example be a multi-level memory cell.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.