Ran Ginosar
25Patents
12h-index
32Co-inventors
81Inventor score
Filing activity: Jan 15, 1991 → Feb 13, 2018
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6600726B1 | Multiple wireless communication protocol methods and apparatuses | Electricity | 160 | Expired |
| US5247366A | Color wide dynamic range camera | Electricity | 129 | Expired |
| US5812993A | Digital hardware architecture for realizing neural network | Physics | 78 | Expired |
| US5202987A | High flow-rate synchronizer/scheduler apparatus and method for multiprocessors | Physics | 69 | Expired |
| US5144442A | Wide dynamic range camera | Electricity | 68 | Expired |
| US5931944A | Branch instruction handling in a self-timed marking system | Physics | 25 | Expired |
| US5948096A | Apparatus and method for self-timed marking of variable length instructions having length-affecting prefix bytes | Physics | 22 | Expired |
| US5420637A | Dynamic image representation system | Electricity | 22 | Expired |
| US7098899B1 | Dual form low power, instant on and high performance, non-instant on computing device | Physics | 20 | Expired |
| US6891857B1 | Multiple wireless communication protocol methods and apparatuses including proactive reduction of interference | Electricity | 18 | Expired |
| US7239615B2 | Multiple wireless communication protocol methods and apparatuses | Electricity | 16 | Expired |
| US5467123A | Apparatus & method for enhancing color images | Electricity | 13 | Expired |
| US6314553A | Circuit synthesis and verification using relative timing | Physics | 11 | Expired |
| US5978899A | Apparatus and method for parallel processing and self-timed serial marking of variable length instructions | Physics | 11 | Expired |
| US10996959B2 | Hybrid processor | Emerging Cross-Sectional Technologies | 10 | Active |
| US5941982A | Efficient self-timed marking of lengthy variable length instructions | Physics | 8 | Expired |
| US8090674B2 | Integrated system and method for multichannel neuronal recording with spike/LFP separation, integrated A/D conversion and threshold detection | Physics | 6 | Active |
| US9449225B2 | Low power hardware algorithms and architectures for spike sorting and detection | Physics | 4 | Active |
| US6931474B1 | Dual-function computing system having instant-on mode of operation | Physics | 4 | Expired |
| US7554475B2 | Low-power inverted ladder digital-to-analog converter | Electricity | 4 | Expired |
| US7096309B2 | Computing device capable of instant-on and non-instant on modes of operation | Physics | 3 | Expired |
| US10366752B2 | Programming for electronic memories | Physics | 2 | Active |
| US8225265B2 | Logic circuit delay optimization | Physics | 1 | Active |
| US10878906B2 | Resistive address decoder and virtually addressed memory | Physics | 0 | Active |
| US10025896B2 | Exploiting the scan test interface for reverse engineering of a VLSI device | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.