Block read count voltage adjustment

US10366763B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Harish Reddy Singidi · Fremont, US
• Kishore Kumar Muchherla · Fremont, US
• Gianni Stephen Alsasua · Rancho Cordova, US
• Ashutosh Malshe · Fremont, US
• Sampath K. Ratnam · Boise, US
• Gary F. Besinga · Boise, US
• Michael G. Miller · Boise, US

Key dates

• Filing date: Oct 31, 2017
• Grant date: Jul 30, 2019
• Expiry date: Oct 31, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C16/08
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

Disclosed in some examples, are methods, systems, and machine readable mediums which compensate for read-disturb effects by shifting the read voltages used to read the value in a NAND cell based upon a read counter. For example, the NAND memory device may have a read counter that corresponds to a group of NAND cells (e.g., a page, a block, a superblock). Anytime a NAND cell in the group is read, the read counter may be incremented. The read voltage, Vread, may be adjusted based on the read counter to account for the read disturb voltage.