Integrated circuit structure with guard ring
US10366916B2 · kind B2 · utility
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1References
20Claims
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Assignee
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Key dates
| Filing date | Mar 12, 2018 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Mar 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure includes a substrate having a first region and a second region being adjacent each other; a first patterned layer formed on the substrate, wherein the first patterned layer includes first features in the first region, wherein the second region is free of the patterned layer; and a first guard ring disposed in the second region and surrounding the first features, wherein the first guard ring includes a first width W1 and is spaced a first distance D1 from the first features, W1 being greater than D1.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.