Bottom-up selective dielectric cross-linking to prevent via landing shorts
US10366950B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2015 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Jun 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L23/53295
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention include an interconnect structure with a via and methods of forming such structures. In an embodiment, the interconnect structure comprises a first interlayer dielectric (ILD). A first interconnect line and a second interconnect line extend into the first ILD. According to an embodiment, a second ILD is positioned over the first interconnect line and the second interconnect line. A via may extend through the second ILD and electrically coupled to the first interconnect line. Additionally, embodiments of the invention include a portion of a bottom surface of the via being positioned over the second interconnect line. However, an isolation layer may be positioned between the bottom surface of the via and a top surface of the second interconnect line, according to an embodiment of the invention.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.