Vertical non-volatile memory device and method for fabricating the same
US10367003B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 12, 2017 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Apr 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/83
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A vertical non-volatile memory device includes a substrate including a cell region; a lower insulating layer on the substrate; a lower wiring pattern in the cell region having a predetermined pattern and connected to the substrate through the lower insulating layer; and a plurality of vertical channel layers extending in a vertical direction with respect to a top surface of the substrate in the cell region, spaced apart from one another in a horizontal direction with respect to the top surface of the substrate, and electrically connected to the lower wiring pattern. The memory device also includes a plurality of gate electrodes stacked alternately with interlayer insulating layers in the cell region in the vertical direction along a side wall of a vertical channel layer and formed to extend in a first direction along the horizontal direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.