Patent · US Active

Sequential integration process

US10367031B2 · kind B2 · utility

1Cited by

5References

12Claims

0Family size

Assignee

IMEC VZW · BE

Inventors

Amey Mahadev Walke · Heverlee, BE
Anne Vandooren · Mazy, BE
Nadine Collaert · Blanden, BE

Key dates

Filing date	Sep 12, 2017
Grant date	Jul 30, 2019
Priority date	—
Expiry date	Sep 12, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10F77/206
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A sequential integration process is described. An example process involves forming a wafer stack by bonding a first wafer to a second wafer with a front side of the first wafer facing a front side of the second wafer, the first wafer including a first device region formed on the front side of the first wafer and including a set of semiconductor devices. The example process involves, subsequent to forming the wafer stack, forming a second device region on a back side of the first wafer, the second device region including a set of semiconductor devices. The example process involves forming at least one interconnection layer on the second device region for electrically interconnecting the semiconductor devices of the second device region. The example process also involves forming at least one via extending through the wafer stack from the at least one interconnection layer and through the first wafer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.