Phase calibration of clock signals
US10367636B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 10, 2018 |
| Grant date | Jul 30, 2019 |
| Priority date | — |
| Expiry date | Oct 10, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2025/03802
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A receiver with clock phase calibration is disclosed. A first sampling circuit generates first digital data based on an input signal, a sampling phase of the first sampling circuit controlled by a first clock signal. A second sampling circuit generates second digital data based on the input signal, a sampling phase of the second sampling circuit controlled by a second clock signal. Circuitry within the receiver calibrates the clocks in different stages. During a first calibration stage, a phase of the second clock signal is adjusted while the first digital data is selected for generating the output data. During a second calibration stage, a phase of the first clock signal is adjusted while the first digital data is selected for the output data path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.