Tensor processor instruction set architecture
US10372456B2 · kind B2 · utility
9Cited by
9References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 2017 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Aug 30, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06N3/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A hardware accelerator having an efficient instruction set is disclosed. An apparatus may comprise logic configured to access a first and a second machine instruction. The second machine instruction may be missing a tensor operand needed to execute the second machine instruction. The logic may be further configured to execute the first machine instruction, resulting in a tensor. The logic may be further configured to execute the second machine instruction using the resultant tensor as the missing tensor operand.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.