Mechanism to support variable size page translations
US10372621B2 · kind B2 · utility
0Cited by
1References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 5, 2018 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Jan 5, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/68
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus to facilitate page translation is disclosed. The apparatus a set associative translation lookaside buffer (TLB) including a plurality of entries to store virtual to physical memory address translations and a page size table (PST) including a plurality of entries to store page size corresponding to each of the TLB entries.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.