Data processing system to implement wiring/silicon blockages via parameterized cells

US10372866B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Christopher J. Berry · Hudson, US
• Adam R. Jatkowski · Wyoming, US
• Frank Malgioglio · Hopewell Junction, US
• Ryan M. Nett · Austin, US
• Joseph J. Palumbo · Poughkeepsie, US
• Sean James Salisbury · Appley Bridge, GB
• Gerald Strevig, III · Cedar Park, US

Key dates

• Filing date: Feb 13, 2017
• Grant date: Aug 6, 2019
• Expiry date: Aug 6, 2037

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F2111/04
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A data processing system to implement wiring/silicon blockages via parameterized cells (pCells) includes a front end-of-line placement/blockage (FEOL P/B) controller to generate a placement blockage based on an input parameter corresponding to a physical design of an integrated circuit (IC). The FEOL P/B outputs a placement blockage parameter that is stored in a wire track allocation database to indicate the placement blockage. A back end-of-line wiring track (BEOL WT) controller generates a wire track blockage of the IC. A BEOL power track (BEOL PT) controller generates a metal blockage within the wire track blockage. A combination of the metal blockage and the wire track blockage defines a parent-child contract to enable concurrent physical design of the IC without creating shorts and overlaps in a child block of the IC.