Christopher J. Berry
52Patents
4h-index
71Co-inventors
69Inventor score
Filing activity: Jun 8, 1989 → Aug 3, 2021
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US5064681A | Selective deposition process for physical vapor deposition | Electricity | 7 | Expired |
| US7739538B2 | Double data rate chaining for synchronous DDR interfaces | Physics | 7 | Active |
| US7735051B2 | Method for replicating and synchronizing a plurality of physical instances with a logical master | Physics | 5 | Active |
| US7987400B2 | Method for optimizing scan chains in an integrated circuit that has multiple levels of hierarchy | Physics | 5 | Active |
| US8006213B2 | Optimization method of integrated circuit design for reduction of global clock load and balancing clock skew | Physics | 4 | Active |
| US7827513B2 | Buffer placement with respect to data flow direction and placement area geometry in hierarchical VLS designs | Physics | 3 | Active |
| US9734268B2 | Slack redistribution for additional power recovery | Physics | 3 | Active |
| US7269806B2 | Decoupling capacitance analysis method | Physics | 3 | Expired |
| US7086026B2 | Decoupling capacitance analysis method | Physics | 2 | Expired |
| US9858377B2 | Constraint-driven pin optimization for hierarchical design convergence | Physics | 2 | Active |
| US9703920B2 | Intra-run design decision process for circuit synthesis | Physics | 2 | Active |
| US7752475B2 | Late data launch for a double data rate elastic interface | Physics | 2 | Active |
| US10157255B2 | Hierarchically aware interior pinning for large synthesis blocks | Physics | 2 | Active |
| US9443048B2 | Physical aware technology mapping in synthesis | Physics | 2 | Active |
| US9910952B2 | Hierarchically aware interior pinning for large synthesis blocks | Physics | 2 | Active |
| US9934341B2 | Simulation of modifications to microprocessor design | Physics | 2 | Active |
| US7469399B2 | Semi-flattened pin optimization process for hierarchical physical designs | Physics | 2 | Active |
| US8799846B1 | Facilitating the design of a clock grid in an integrated circuit | Physics | 2 | Active |
| US10943051B1 | Metal fill shape removal from selected nets | Physics | 1 | Active |
| US9715572B2 | Hierarchical wire-pin co-optimization | Physics | 1 | Active |
| US9659140B2 | Critical region identification | Physics | 1 | Active |
| US10372866B2 | Data processing system to implement wiring/silicon blockages via parameterized cells | Physics | 1 | Active |
| US7921399B2 | Method for simplifying tie net modeling for router performance | Physics | 1 | Active |
| US9881100B2 | Scoping searches within websites | Physics | 1 | Active |
| US7346877B2 | Decoupling capacitance analysis method | Physics | 1 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.