Patent · US Active

In-design real-time electrical impact verification flow

US10372867B2 · kind B2 · utility

0Cited by

2References

16Claims

0Family size

Assignee

SYNOPSYS, INC. · US

Inventors

Jun Wang · Sunnyvale, US
Randy Bishop · Broomfield, US
Jingyu Xu · San Jose, US
Dick Liu · Saratoga, US
Hu Cai · Shanghai, CN
Jun Lu · Beijing, CN

Key dates

Filing date	Sep 2, 2015
Grant date	Aug 6, 2019
Priority date	—
Expiry date	Sep 2, 2035

Classification

Technology area (CPC G)Physics
CPC primaryG06F30/394
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Techniques for analyzing a routed interconnection of a net of a circuit are discussed herein. Some embodiments may include a method comprising with a computer, analyzing the circuit to determine a performance parameter of the net, wherein the circuit is analyzed based at least in part on applying pre-layout simulation data of the net to layout data of the circuit. Additionally or alternatively, the circuit may be analyzed based on extracting characteristics of the routed interconnection from the layout data of the net.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.