IC layout post-decomposition mask allocation optimization
US10372871B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 28, 2017 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Nov 9, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/18
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
An IC design layout is decomposed into multiple masks to produce an initial output. A post-decomposition optimization is performed. The post-decomposition optimization includes identifying hotspots in the multiple masks, clustering features that contribute to the hotspots into clusters, identifying ones of the clusters that can be relocated to a different mask to eliminate the hotspot, without violating design rules, as reversible clusters, ranking movement of the reversible clusters by comparing the reversible clusters, as potentially moved, to known manufacturability metrics, and moving the reversible clusters to different masks according to the priority established by the ranking, to produce a post-decomposition optimized tape-out. The IC devices are manufactured by applying the post-decomposition optimized tape-out to manufacturing equipment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.