Apparatuses and methods for duty cycle distortion correction of clocks
US10373660B1 · kind B1 · utility
2Cited by
7References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 2019 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Feb 13, 2039 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1565
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods for duty cycle distortion correction of clocks are disclosed. An example apparatus includes a clock circuit configured to receive complementary input clocks and a control signal and to provide multiphase clocks responsive to complementary input clocks. The clock circuit is further configured to be in a first mode or second mode controlled by the control signal and configured to provide the multiphase clocks having greater duty cycle distortion in a first mode than in a second mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.