Patent · US Active

Electronic package assembly with compact die placement

US10373888B2 · kind B2 · utility

2Cited by

1References

13Claims

0Family size

Assignee

Intel Corporation · US

Inventors

Eric J. Li · Chandler, US
Vipul V. Mehta · Chandler, US
Digvijay A. Raorane · Chandler, US

Key dates

Filing date	Dec 30, 2016
Grant date	Aug 6, 2019
Priority date	—
Expiry date	Dec 30, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/18161
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

An electronic package assembly is disclosed. A substrate can have an upper surface area. A first active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A second active die can have an upper surface area and a bottom surface, the bottom surface operably coupled to the substrate. A capillary underfill material can at least partially encapsulate the bottom surface of the first active die and the second active die and extend upwardly upon inside side surfaces of the first and second active dies. A combined area of the upper surface area of the first active die and an upper surface area of the second active die is at least about 90% of the upper surface area of the substrate.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.