Semiconductor package
US10373935B2 · kind B2 · utility
2Cited by
11References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 28, 2018 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Aug 28, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2225/06582
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes: a first semiconductor chip in which a through-electrode is provided; a second semiconductor chip connected to a top surface of the first semiconductor chip; a first connection bump attached to a bottom surface of the first semiconductor chip and including a first pillar structure and a first solder layer; and a second connection bump located between the first semiconductor chip and the second semiconductor chip, configured to electrically connect the first semiconductor chip and the second semiconductor chip, and including a second pillar structure and a second solder layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.