Semiconductor device including a semiconductor extension layer between active regions
US10373953B2 · kind B2 · utility
3Cited by
4References
11Claims
0Family size
Assignee
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Key dates
| Filing date | May 19, 2016 |
| Grant date | Aug 6, 2019 |
| Priority date | — |
| Expiry date | Oct 14, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/83
Abstract
A semiconductor device includes a first active region and a second active region, which are disposed in a semiconductor substrate and have side surfaces facing each other, an isolation pattern disposed between the first and second active regions, a semiconductor extension layer disposed between the first and second active regions, a first source/drain semiconductor layer disposed on the first active region, and a second source/drain semiconductor layer disposed on the second active region. The facing side surfaces of the first and second active regions are closer to the semiconductor extension layer than the isolation pattern.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.