Asymmetric error correction and flash-memory rewriting using polar codes
US10379945B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 14, 2015 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Jan 14, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M13/154
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Techniques are disclosed for generating codes for representation of data in memory devices that may avoid the block erasure operation in changing data values. Data values comprising binary digits (bits) can be encoded and decoded using the generated codes, referred to as codewords, such that the codewords may comprise a block erasure-avoiding code, in which the binary digits of a data message m can be encoded such that the encoded data message can be stored into multiple memory cells of a data device and, once a memory cell value is changed from a first logic value to a second logic value, the value of the memory cell may remain at the second logic value, regardless of subsequently received messages, until a block erasure operation on the memory cell. Similarly, a received data message comprising an input codeword, in which source data values of multiple binary digits have been encoded with the disclosed block erasure-avoiding code, can be decoded in the data device to recover an estimated source data message.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.