Semiconductor memory device with burst mode
US10381066B2 · kind B2 · utility
3Cited by
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24Claims
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Key dates
| Filing date | Sep 18, 2017 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Sep 18, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor device may include a data input and output circuit (I/O) configured to selectively or simultaneously drive input and output lines according to a burst length and a location of a memory area selected by an address to allow the semiconductor device to receive or output data regardless of the burst length being changed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.