Patent · US Active

Semiconductor device package including filling mold via

US10381300B2 · kind B2 · utility

4Cited by
2References
26Claims
0Family size

Assignee

Inventors

Key dates

Filing dateNov 28, 2016
Grant dateAug 13, 2019
Priority date—
Expiry dateNov 28, 2036

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH01L2924/19106
  • WIPO fieldSemiconductors
  • WIPO sectorElectrical engineering

Abstract

A semiconductor device package includes a substrate, a package body, a via and an interconnect. The substrate includes a surface and a pad on the first surface. The package body covers at least a portion of the surface of the substrate. The via is disposed in the package body and includes a conductive layer and a first intermediate layer. The conductive layer is electrically connected with the pad. The first intermediate layer is adjacent to the conductive layer. The interconnect is disposed on the first intermediate layer.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.