Semiconductor package and method of manufacturing the semiconductor package
US10381334B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 18, 2017 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Oct 18, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/217
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor package includes a package substrate having an upper surface and a lower surface and including a plurality of substrate pads formed on the upper surface, a capacitor structure arranged on the upper surface of the package substrate and including a semiconductor substrate and at least one decoupling capacitor formed in the upper surface of the semiconductor substrate, a plurality of first semiconductor chips mounted on the package and supported by the capacitor structure, first conductive connection members electrically connecting chip pads of the first semiconductor chips to the substrate pads, and second conductive connection members electrically connecting capacitor pads of the decoupling capacitor to the substrate pad.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.