Three-dimensional phase change memory array including discrete middle electrodes and methods of making the same
US10381409B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 7, 2018 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Jun 7, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N70/066
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Alternating stacks of insulating strips and sacrificial material strips are formed over a substrate. A laterally alternating sequence of pillar cavities and pillar structures can be formed within each of the line trenches. A phase change memory cell including a discrete metal portion, a phase change memory material portion, and a selector material portion is formed at each level of the sacrificial material strips at a periphery of each of the pillar cavities. Vertical bit lines are formed in the two-dimensional array of pillar cavities. Remaining portions of the sacrificial material strips are replaced with electrically conductive word line strips. Pathways for providing an isotropic etchant for the sacrificial material strips and a reactant for a conductive material of the electrically conductive word line strips may be provided by a backside trench, or by removing the pillar structures to provide backside openings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.