Method for fabricating asymmetrical three dimensional device
US10381465B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 18, 2015 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Nov 28, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/26586
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming an asymmetrical three dimensional semiconductor device. The method may include providing a fin structure extending perpendicularly from a substrate plane and having a fin axis parallel to the substrate plane, wherein a portion of the fin structure is covered by a gate structure defining a channel region, and wherein the fin structure comprises a first end surface not covered by the gate structure and second end surface not covered by the gate structure. The method may further include directing ions in a fin treatment to the fin structure, wherein the fin treatment comprises a first treatment of the first end surface and a second treatment of the second end surface different from the first treatment.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.