Inventor · San Jose, CA, US

Benjamin Colombeau

48Patents
4h-index
81Co-inventors
62Inventor score

Filing activity: Sep 27, 2007 → Oct 18, 2022

Most-cited inventions

PatentTitleAreaCited byStatus
US8053340B2 Method for fabricating semiconductor devices with reduced junction diffusion Electricity 97 Active
US9853129B2 Forming non-line-of-sight source drain extension in an nMOS finFET using n-doped selective epitaxial growth Electricity 17 Active
US9460920B1 Horizontal gate all around device isolation Electricity 11 Active
US9396902B2 Gallium ION source and materials therefore Electricity 8 Active
US9865735B2 Horizontal gate all around and FinFET device isolation Electricity 4 Active
US8354321B2 Method for fabricating semiconductor devices with reduced junction diffusion Electricity 4 Active
US8722431B2 FinFET device fabrication using thermal implantation Electricity 4 Active
US8999800B2 Method of reducing contact resistance Electricity 4 Active
US10861722B2 Integrated semiconductor processing Electricity 3 Active
US10573719B2 Horizontal gate all around device isolation Electricity 2 Active
US9455196B2 Method for improving fin isolation Electricity 2 Active
US10381465B2 Method for fabricating asymmetrical three dimensional device Electricity 2 Active
US8860142B2 Method and apparatus to reduce thermal variations within an integrated circuit die using thermal proximity correction Electricity 2 Active
US9748364B2 Method for fabricating three dimensional device Electricity 1 Active
US11309404B2 Integrated CMOS source drain formation with advanced control Electricity 1 Active
US8012843B2 Optimized halo or pocket cold implants Electricity 1 Active
US10490666B2 Horizontal gate all around and FinFET device isolation Electricity 1 Active
US10347462B2 Imaging of crystalline defects Electricity 1 Active
US11393916B2 Methods for GAA I/O formation by selective epi regrowth Electricity 1 Active
US12027607B2 Methods for GAA I/O formation by selective epi regrowth Electricity 1 Active
US9337314B2 Technique for selectively processing three dimensional device Electricity 0 Active
US12261047B2 Doping techniques Electricity 0 Active
US10629752B1 Gate all-around device Electricity 0 Active
US11495500B2 Horizontal GAA nano-wire and nano-slab transistors Electricity 0 Active
US10483355B2 Forming non-line-of-sight source drain extension in an NMOS FINFET using n-doped selective epitaxial growth Electricity 0 Active

Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.