Multi-layer circuit structure and manufacturing method thereof
US10383226B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 11, 2017 |
| Grant date | Aug 13, 2019 |
| Priority date | — |
| Expiry date | Dec 11, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/107
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A multi-layer circuit structure including a core layer, a first circuit structure, a second circuit structure, and a build-up circuit structure is provided. The first circuit structure and the second circuit structure are respectively disposed on two opposite surfaces of the core layer. The build-up circuit structure includes a first dielectric layer disposed on the first circuit structure, first conductive blind holes, a second dielectric layer disposed on the first dielectric layer, second conductive blind holes, and a patterned circuit layer disposed on the second dielectric layer. The first conductive blind holes penetrate through the first dielectric layer and electrically contact the first circuit structure. The second conductive blind holes penetrate through the second dielectric layer and electrically contact the first conductive blind holes respectively. The patterned circuit layer electrically contacts the second conductive blind holes. A manufacturing method of the multi-layer circuit structure is also provided.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.