Method for continuous tester operation during multiple stage temperature testing
US10386405B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 2, 2017 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Nov 11, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/5002
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method is provided for performing continuous single insertion semiconductor testing of a group of semiconductors that are divided into a first subgroup and a second subgroup at multiple different temperatures. The single insertion semiconductor testing is performed by sequentially executing testing cycles, characterized by the tester alternately executing temperature testing periods and temperature ramping periods for the first subgroup, while simultaneously executing temperature ramping periods and temperature testing periods for the second subgroup. The temperature testing periods operate at two or more different temperatures. The single insertion testing sequence entirely eliminates tester index time when the testing time is equal to or greater than the ramping times, and substantially reduces tester index time when the testing time is less that the ramping times.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.