Memory circuit with improved read and write access
US10387047B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 2016 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Nov 21, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/2236
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit includes a plurality of banks and a controller, each bank of the plurality of banks includes a plurality of segments, and each segment of the plurality of segments includes a plurality of bit lines and a plurality of word lines. A word line switch corresponding to a word line of a segment of the memory circuit is turned on and data are written into memory cells of the segment coupled to a plurality of bit lines of the segment and corresponding to the word line in turn after the controller enables an active command corresponding to the word line. When the controller enables at least one copy row write command, the data are simultaneously written into memory cells sharing a plurality of sense amplifiers with the plurality of bit lines of the segment and corresponding to at least one another word line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.