Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks
US10387151B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 2011 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | May 21, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatus are disclosed for accessing multiple data cache lines for scatter/gather operations. Embodiment of apparatus may comprise address generation logic to generate an address from an index of a set of indices for each of a set of corresponding mask elements having a first value. Line or bank match ordering logic matches addresses in the same cache line or different banks, and orders an access sequence to permit a group of addresses in multiple cache lines and different banks. Address selection logic directs the group of addresses to corresponding different banks in a cache to access data elements in multiple cache lines corresponding to the group of addresses in a single access cycle. A disassembly/reassembly buffer orders the data elements according to their respective bank/register positions, and a gather/scatter finite state machine changes the values of corresponding mask elements from the first value to a second value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.