Sailesh Kottapalli
33Patents
7h-index
54Co-inventors
72Inventor score
Filing activity: Aug 6, 1998 → Feb 11, 2020
Most-cited inventions
| Patent | Title | Area | Cited by | Status |
|---|---|---|---|---|
| US6304960A | Validating prediction for branches in a cluster via comparison of predicted and condition selected tentative target addresses and validation of branch conditions | Physics | 43 | Expired |
| US6898694B2 | High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle | Physics | 42 | Expired |
| US7062933B2 | Separate thermal and electrical throttling limits in processors | Emerging Cross-Sectional Technologies | 26 | Expired |
| US7984248B2 | Transaction based shared data operations in a multiprocessor environment | Physics | 17 | Expired |
| US7500240B2 | Apparatus and method for scheduling threads in multi-threading processors | Physics | 11 | Expired |
| US7149880B2 | Method and apparatus for instruction pointer storage element configuration in a simultaneous multithreaded processor | Physics | 10 | Expired |
| US9858167B2 | Monitoring the operation of a processor | Physics | 10 | Active |
| US7669009B2 | Method and apparatus for run-ahead victim selection to reduce undesirable replacement behavior in inclusive caches | Physics | 6 | Expired |
| US8473963B2 | Synchronizing multiple threads efficiently | Physics | 6 | Active |
| US8656115B2 | Extending a cache coherency snoop broadcast protocol with directory information | Physics | 6 | Active |
| US7996644B2 | Fair sharing of a cache in a multi-core/multi-threaded processor by dynamically partitioning of the cache | Physics | 6 | Expired |
| US7496732B2 | Method and apparatus for results speculation under run-ahead execution | Physics | 4 | Expired |
| US7181590B2 | Method for page sharing in a processor with multiple threads and pre-validated caches | Physics | 4 | Expired |
| US7401211B2 | Method for converting pipeline stalls caused by instructions with long latency memory accesses to pipeline flushes in a multithreaded processor | Physics | 3 | Expired |
| US7937709B2 | Synchronizing multiple threads efficiently | Physics | 3 | Active |
| US8176266B2 | Transaction based shared data operations in a multiprocessor environment | Physics | 3 | Active |
| US9201748B2 | Virtual device sparing | Physics | 2 | Active |
| US9423959B2 | Method and apparatus for store durability and ordering in a persistent memory architecture | Physics | 2 | Active |
| US7149881B2 | Method and apparatus for improving dispersal performance in a processor through the use of no-op ports | Physics | 2 | Expired |
| US10387151B2 | Processor and method for tracking progress of gathering/scattering data element pairs in different cache memory banks | Physics | 2 | Active |
| US8301907B2 | Supporting advanced RAS features in a secured computing system | Physics | 1 | Active |
| US9405595B2 | Synchronizing multiple threads efficiently | Physics | 1 | Active |
| US8458412B2 | Transaction based shared data operations in a multiprocessor environment | Physics | 1 | Active |
| US8205204B2 | Apparatus and method for scheduling threads in multi-threading processors | Physics | 1 | Active |
| US8819684B2 | Synchronizing multiple threads efficiently | Physics | 0 | Active |
Source: USPTO / EPO open patent data. Inventor disambiguation is heuristic; counts are objective bibliographic measures.