High performance interconnect physical layer
US10387339B2 · kind B2 · utility
2Cited by
7References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2016 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Apr 6, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L49/15
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A supersequence corresponding to an initialization state is received on a link that includes a repeating pattern of an electrical idle exit ordered set (EIEOS) followed by a number of consecutive training sequences. Instances of the EIEOS are to be aligned with a rollover of a sync counter. A latency value is determined from one of the EIEOS instances in the supersequence and latency is added to a receive path of the link through a latency buffer based on the latency value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.