Patent · US Active

System and method for managing and composing verification engines

US10387605B2 · kind B2 · utility

2Cited by
11References
21Claims
0Family size

Assignee

Inventors

Key dates

Filing dateJul 23, 2015
Grant dateAug 20, 2019
Priority date
Expiry dateMay 9, 2037

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG06F30/3323
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

A system and method for managing and composing verification engines and simultaneously applying such compositions to verify properties with design constraints allocates computing resources to verification engines based upon properties to be checked and optionally a user-specified budget. The verification engines are run in order to verify a received register transfer level (RTL) design description of a circuit according to user-specified assertions and constraints received by the system. The particular verification engines to be run are selected from a database of such engines and a run order is designated in sequential, parallel and distributed flows.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.