Semiconductor memory system
US10388640B2 · kind B2 · utility
0Cited by
6References
14Claims
0Family size
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Key dates
| Filing date | Nov 24, 2017 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Nov 24, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02P70/50
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
According to one embodiment, a semiconductor memory system includes a substrate, a plurality of elements and an adhesive portion. The substrate has a multilayer structure in which wiring patterns are formed, and has a substantially rectangle shape in a planar view. The elements are provided and arranged along the long-side direction of a surface layer side of the substrate. The adhesive portion is filled in a gap between the elements and in a gap between the elements and the substrate, where surfaces of the elements are exposed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.