Wiring line structure of three-dimensional memory device
US10388663B2 · kind B2 · utility
8Cited by
0References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2018 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Jan 24, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B43/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a substrate, channel structures disposed over the substrate and extending in a first direction perpendicular to a top surface of the substrate, a plurality of gate lines surrounding the channel structures and stacked over the substrate along the first direction, and a wiring line disposed at the same layer as at least one of the gate lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.