Vertical transport FET (VFET) with dual top spacer

US10388766B2 · kind B2 · utility

Assignee

• International Business Machines Corporation · US

Inventors

• Shogo Mochizuki · Clifton Park, US
• Michael P. Belyansky · Hopewell Junction, US
• Choonghyun Lee · Rensselaer, US

Key dates

• Filing date: Oct 23, 2017
• Grant date: Aug 20, 2019
• Expiry date: Oct 23, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/151

Abstract

A VFET device with a dual top spacer to prevent source/drain-to-gate short, and techniques for formation thereof are provided. In one aspect, a method of forming a VFET device includes: etching vertical fin channels in a substrate; forming a bottom source and drain in the substrate beneath the vertical fin channels; forming a bottom spacer on the bottom source and drain; depositing a gate dielectric and gate conductor onto the vertical fin channels; recessing the gate dielectric and gate conductor to expose tops of the vertical fin channels; selectively forming dielectric spacers on end portions of the gate dielectric and gate conductor adjacent to the tops of the vertical fin channels; depositing an encapsulation layer onto the vertical fin channels; recessing the encapsulation layer with the dielectric spacers serving as an etch stop; and forming top source and drains. A VFET device formed using the present techniques is also provided.