Semiconductor circuit
US10389367B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 26, 2018 |
| Grant date | Aug 20, 2019 |
| Priority date | — |
| Expiry date | Feb 26, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2213/0026
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor circuit includes a plurality of transmitting circuits, each of which receives a corresponding one of synchronized first clock signals input thereto and includes a first circuit outputting a third clock signal which is generated by dividing the frequency of an unsynchronized second clock signal and is synchronized with the first clock signal, a phase comparator comparing phases of the first clock signal and the third clock signal, and a reset signal generator setting, if a phase shift is detected by the phase comparator, the first signal at a first logic level for a predetermined period. The first circuit enters a reset state during a period in which the first signal is at the first logic level, and, when the first signal changes from the first logic level to a second logic level, is released from a reset state and generates the third clock signal synchronized with the first clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.