Clock selection circuit and test clock generation circuit for LBIST and ATPG test circuit

US10393804B2 · kind B2 · utility

Assignee

• STMicroelectronics International N.V. · NL

Inventors

• Venkata Narayanan Srinivasan · Greater Noida, IN
• Nimit Endlay · Greater Noida, IN
• Balwinder Singh Soni · Faridabad, IN

Key dates

• Filing date: Oct 25, 2018
• Grant date: Aug 27, 2019
• Expiry date: Oct 25, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F11/27
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A test circuit is operable in ATPG mode and LBIST mode. The test circuit includes a clock selection circuit. The clock selection circuit includes clock logic circuitry to receive an LBIST mode signal and an ATPG mode signal and to generate an indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode, a multiplexing circuit to receive an ATPG clock and a functional clock as input and output a selected one of the ATPG clock and the functional clock, and a clock gate circuit enabled in response to enable signals. The enable signals are an inverse of a selected one of the ATPG clock and the functional clock. The clock gate circuit receives the indication of whether the test circuit is operating in either the ATPG mode or the LBIST mode and generates a test clock as a function of the indication.