Wait and poll instructions for monitoring a plurality of addresses
US10394678B2 · kind B2 · utility
2Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 29, 2016 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Dec 29, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A processor core includes a decode circuit to decode an instruction. The processor core further includes a monitor circuit, where the monitor circuit includes a data structure to store a plurality of entries for addresses that are being monitored by the monitor circuit and a triggered queue to store a plurality of addresses for which a triggering event occurred. The processor core further includes an execution circuit to execute the decoded instruction to dequeue an address from the triggered queue and return the dequeued address in response to a determination that the triggered queue is not empty.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.