Apparatuses and methods for duty cycle error correction of clock signals
US10395704B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 22, 2017 |
| Grant date | Aug 27, 2019 |
| Priority date | — |
| Expiry date | Dec 22, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/028
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatuses and methods for duty cycle error correction of clock signals are disclosed. An example method includes detecting a clock period error between a first clock signal and a third clock signal and adjusting a timing of the first or third clock signals based on the clock period error therebetween. The method further includes detecting a clock period error between a second clock signal and a fourth clock signal and adjusting a timing of the second or fourth clock signals based on the clock period error therebetween. Additionally, the example method includes detecting a duty cycle error between the first, second, third, and fourth clock signals, and adjusting a timing of the first and third or second and fourth clock signals based on the duty cycle error therebetween.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.