Method of patterning target layer

US10395978B2 · kind B2 · utility

Assignee

• IMEC VZW · BE

Inventors

• Basoene Briggs · Heverlee, BE
• Farid Sebaai · Saint-Martin-d'Hères, FR
• Juergen Boemmels · Heverlee, BE
• Zsolt Tokei · Leuven, BE
• Christopher Wilson · Tervuren, BE
• Katia Devriendt · Binkom, BE

Key dates

• Filing date: Feb 27, 2018
• Grant date: Aug 27, 2019
• Expiry date: Feb 27, 2038

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/32139
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

The disclosed technology generally relates to semiconductor processing, and more particularly to patterning a target layer using a sacrificial structure. According to an aspect of the disclosed technology, a method of patterning a target layer comprises forming on the target layer a plurality of parallel material lines spaced apart such that longitudinal gaps exposing the target layer are formed between the material lines. The method additionally includes filling the gaps with a sacrificial material and forming a hole by removing the sacrificial material along a portion of one of the gaps, where the hole extends across the gap. The hole exposes the target layer in the gap. The method additionally includes filling the hole with a fill material to form a block portion extending across the gap. The method additionally includes removing, selectively to the material lines and the block portion, the sacrificial material from the target layer to expose the gaps, where the one of the gaps is interrupted in the longitudinal direction by the block portion. The method further includes transferring a pattern including the material lines and the block portion into the target layer.